MIPS based 5-stage pipeline processor
A simple processor based on MIPS ISA, which is written in Verilog and has a 5-stage pipeline
A simple processor based on MIPS ISA, which is written in Verilog and has a 5-stage pipeline
This is the project that I am working on to construct an accelerator on the vck190 board to efficiently enhance the performance of the large point FFT operation.
Published in DAC-WIP 2024, 2024
This paper is about efficiently and automatically implementing a scalable FFT on the Versal ACAP.
Recommended citation: Hao Yang, Linfeng Du, and Wei Zhang. “ESFA: An Efficient Scalable FFT Accelerator Design Framework on Versal AI Engine,” DAC-WIP 2024.
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